Brent Bean
40Patents
5h-index
12Co-inventors
66Inventor score
Filing activity: Apr 6, 1992 → Nov 3, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7203824B2 | Apparatus and method for handling BTAC branches that wrap across instruction cache lines | Physics | 23 | Expired |
| US8074060B2 | Out-of-order execution microprocessor that selectively initiates instruction retirement early | Physics | 11 | Active |
| US9967092B2 | Key expansion logic using decryption key primitives | Electricity | 7 | Active |
| US7975132B2 | Apparatus and method for fast correct resolution of call and return instructions using multiple call/return stacks in the presence of speculative conditional instruction execution in a pipelined microprocessor | Physics | 6 | Active |
| US5319213A | Thermal target test board | Physics | 6 | Expired |
| US9798898B2 | Microprocessor with secure execution mode and store key instructions | Electricity | 4 | Active |
| US9911008B2 | Microprocessor with on-the-fly switching of decryption keys | Electricity | 4 | Active |
| US9892283B2 | Decryption of encrypted instructions using keys selected on basis of instruction fetch address | Electricity | 3 | Active |
| US8521996B2 | Pipelined microprocessor with fast non-selective correct conditional branch instruction resolution | Physics | 3 | Active |
| US7234045B2 | Apparatus and method for handling BTAC branches that wrap across instruction cache lines | Physics | 3 | Expired |
| US8719589B2 | Microprocessor that facilitates task switching between multiple encrypted programs having different associated decryption key values | Electricity | 2 | Active |
| US9507404B2 | Single core wakeup multi-core synchronization mechanism | Emerging Cross-Sectional Technologies | 2 | Active |
| US9372696B2 | Microprocessor with compressed and uncompressed microcode memories | Physics | 2 | Active |
| US9461818B2 | Method for encrypting a program for subsequent execution by a microprocessor configured to decrypt and execute the encrypted program | Electricity | 1 | Active |
| US8423751B2 | Microprocessor with fast execution of call and return instructions | Physics | 1 | Active |
| US8645714B2 | Branch target address cache for predicting instruction decryption keys in a microprocessor that fetches and decrypts encrypted instructions | Electricity | 1 | Active |
| US8281110B2 | Out-of-order microprocessor with separate branch information circular queue table tagged by branch instructions in reorder buffer to reduce unnecessary space in buffer | Physics | 1 | Active |
| US8635437B2 | Pipelined microprocessor with fast conditional branch instructions based on static exception state | Physics | 1 | Active |
| US8639945B2 | Branch and switch key instruction in a microprocessor that fetches and decrypts encrypted instructions | Electricity | 1 | Active |
| US8886960B2 | Microprocessor that facilitates task switching between encrypted and unencrypted programs | Electricity | 1 | Active |
| US8131984B2 | Pipelined microprocessor with fast conditional branch instructions based on static serializing instruction state | Physics | 0 | Active |
| US10108431B2 | Method and apparatus for waking a single core of a multi-core microprocessor, while maintaining most cores in a sleep state | Emerging Cross-Sectional Technologies | 0 | Active |
| US8683225B2 | Microprocessor that facilitates task switching between encrypted and unencrypted programs | Electricity | 0 | Active |
| US9483263B2 | Uncore microcode ROM | Physics | 0 | Active |
| US9361097B2 | Selectively compressed microcode | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.