Integrated circuit power management verification method
US8645886B2 · kind B2 · utility
6Cited by
23References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2012 |
| Grant date | Feb 4, 2014 |
| Priority date | — |
| Expiry date | Apr 16, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for verifying power management of an integrated circuit design includes estimating a current load requirement of clocked modules in the circuit design based on the clock frequency and a predefined current load model. The voltage supplied to the circuit design is monitored. A first voltage regulator provides additional current drive to the circuit design when the supplied voltage drops below a threshold value of a full throttle run mode of the circuit design. A second voltage regulator is enabled to boost a response time of the first voltage regulator when the voltage drops below the threshold value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.