Integrated circuit design verification system
US8645897B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2013 |
| Grant date | Feb 4, 2014 |
| Priority date | — |
| Expiry date | Jan 7, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) design verification system includes a memory for storing an IC design and a processor in communication with the memory. The IC design includes multiple IP cores and the design verification apparatus includes multiple verification modules. The processor configures a first set of connections between the IP cores and the verification modules based on a first connection database and verifies each IP core independently using the first set of connections. Thereafter, the processor configures a second set of connections between the IP cores and the verification modules based on a second connection database generated based on the first connection database, and verifies the multiple IP cores together using the second set of connections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.