Wafer level packaging bond
US8647962B2 · kind B2 · utility
10Cited by
3References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2010 |
| Grant date | Feb 11, 2014 |
| Priority date | — |
| Expiry date | Oct 29, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a method of bonding a plurality of substrates. In an embodiment, a first substrate includes a first bonding layer. The second substrate includes a second bonding layer. The first bonding layer includes silicon; the second bonding layer includes aluminum. The first substrate and the second substrate are bonded forming a bond region having an interface between the first bonding layer and the second bonding layer. A device having a bonding region between substrates is also provided. The bonding region includes an interface between a layer including silicon and a layer including aluminum.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.