Structure and method of wafer level chip molded packaging
US8647963B2 · kind B2 · utility
7Cited by
1References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2010 |
| Grant date | Feb 11, 2014 |
| Priority date | — |
| Expiry date | Dec 27, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer is provided having a chip side and a non-chip side, the chip side comprising a plurality of semiconductor chips. A plurality of dies are provided, each of the dies is bonded to one of the plurality of semiconductor chips. One or more trenches are formed on the chip side of the wafer. The chip side of the wafer and the plurality of dies are encapsulated with a protecting material, the protecting material substantially filling the one or more trenches. The wafer is diced to separate it into individual semiconductor packages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.