Memory cell, a method for forming a memory cell, and a method for operating a memory cell
US8649205B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2012 |
| Grant date | Feb 11, 2014 |
| Priority date | — |
| Expiry date | Jul 4, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49117
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell is provided, the memory cell including a first two-terminal memory element; a second two-terminal memory element; a controller circuit configured to program the first two-terminal memory element to one or more states and the second two-terminal memory element to one or more states, wherein a state of the first two-terminal memory element and a state of the second two-terminal memory element are interdependent; and a measuring circuit configured to measure a difference signal between a first two-terminal memory element signal associated with the state of the first two-terminal memory element and a second two-terminal memory element signal associated with the state of the second two-terminal memory element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.