Computer system and method of protection for the system's marking store
US8650437B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2010 |
| Grant date | Feb 11, 2014 |
| Priority date | — |
| Expiry date | Jun 10, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for controlling marking store updates in a central electronic complex with a plurality of core processors and eDRAM cache and interconnect bus to a service processor for loading memory controller firmware to dual-channel DDR3 memory controllers with an internal marking store. Loaded firmware of the memory controllers is responsible for tracking of ECC errors using a ECC decoder control whereby said marking store is written by a slow ECC decoder, and read by a fast ECC decoder for every read operation of said memory controllers to provide a blocking mechanism for notifying marking store firmware when the marking store has been updated and which guarantees that marking store firmware cannot write to the marking store until the marking store firmware has seen updates without causing the marking store hardware to time out.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.