Method and apparatus for low-pin count testing of integrated circuits
US8650524B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2012 |
| Grant date | Feb 11, 2014 |
| Priority date | — |
| Expiry date | Nov 9, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/333
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus to apply compressed test patterns using a very pin-limited test apparatus to a chip design for use in semiconductor manufacturing test is disclosed. Compression circuitry is inserted into the circuit design and the compressed signals manipulated for communication over a serial interface. On a test apparatus, ATPG may be run, assuming a parallel test interface, resulting in test patterns that may be compressed into a parallel format and then converted into a serial signal. On chip, the serial signal is parallelized, decompressed, and then shifted into the scan chains. An inserted controller generates clocks and various control signals. Conventional test patterns from ATPG may be generated and applied during testing without the need to modify the ATPG program saving time and resources. Hierarchical testing of integrated circuits built with a multiplicity of cores, each having its own embedded compression logic, is also supported.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.