Methods for fabricating integrated circuits with narrow, metal filled openings

US8652890B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Sven Schmidbauer · Dresden, DE
• Dina H. Triyoso · Mechanicville, US
• Elke Erben · Dresden, DE
• Hao Zhang · Beijing, CN
• Robert Binder · Dresden, DE

Key dates

• Filing date: Feb 29, 2012
• Grant date: Feb 18, 2014
• Expiry date: Mar 24, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/68
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Methods are provided for fabricating an integrated circuit that includes metal filled narrow openings. In accordance with one embodiment a method includes forming a dummy gate overlying a semiconductor substrate and subsequently removing the dummy gate to form a narrow opening. A layer of high dielectric constant insulator and a layer of work function-determining material are deposited overlying the semiconductor substrate. The layer of work function-determining material is exposed to a nitrogen ambient in a first chamber. A layer of titanium is deposited into the narrow opening in the first chamber in the presence of the nitrogen ambient to cause the first portion of the layer of titanium to be nitrided. The deposition of titanium continues, and the remaining portion of the layer of titanium is deposited as substantially pure titanium. Aluminum is deposited overlying the layer of titanium to fill the narrow opening and to form a gate electrode.