Patent · US Active

Method for 1/F noise reduction in NMOS devices

US8653607B2 · kind B2 · utility

0Cited by

2References

12Claims

0Family size

Assignee

TEXAS INSTRUMENTS INCORPORATED · US

Inventors

Alwin Tsao · Garland, US
Purushothaman Srinivasan · Allen, US

Key dates

Filing date	Jun 14, 2012
Grant date	Feb 18, 2014
Priority date	—
Expiry date	Jun 14, 2032

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/0177
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An integrated circuit, in which a minimum gate length of low-noise NMOS transistors is less than twice a minimum gate length of logic NMOS transistors, is formed by: forming gates of the low-noise NMOS transistors concurrently with gates of the logic NMOS transistors, forming a low-noise NMDD implant mask which exposes the low-noise NMOS transistors and covers the logic NMOS transistors and logic PMOS transistors, ion implanting n-type NMDD dopants and fluorine into the low-noise NMOS transistors and limiting p-type halo dopants to less than 20 percent of a corresponding logic NMOS halo dose, removing the low-noise NMDD implant mask, forming a logic NMDD implant mask which exposes the logic NMOS transistors and covers the low-noise NMOS transistors and logic PMOS transistors, ion implanting n-type NMDD dopants and p-type halo dopants, but not implanting fluorine, into the logic NMOS transistors, and removing the logic NMDD implant mask.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.