FinFET design with reduced current crowding
US8653608B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 2010 |
| Grant date | Feb 18, 2014 |
| Priority date | — |
| Expiry date | Nov 3, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6219
Abstract
An integrated circuit structure includes a substrate and a fin field-effect transistor (FinFET). The FinFET includes a fin over the substrate and having a first fin portion and a second fin portion. A gate stack is formed on a top surface and sidewalls of the first fin portion. An epitaxial semiconductor layer has a first portion formed directly over the second fin portion, and a second portion formed on sidewalls of the second fin portion. A silicide layer is formed on the epitaxial semiconductor layer. A peripheral ratio of a total length of an effective silicide peripheral of the FinFET to a total length of a fin peripheral of the FinFET is greater than 1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.