Method and apparatus for memory power management
US8656198B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 26, 2010 |
| Grant date | Feb 18, 2014 |
| Priority date | — |
| Expiry date | Jul 11, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for power management is disclosed. The method may include monitoring requests for access to a memory of a memory subsystem by one or more processor cores; and monitoring requests for access to the memory conveyed by an input/output (I/O) unit. The method may further include determining if at least a first amount of time has elapsed since any one of the processor cores has asserted a memory access request and determining if at least a second amount of time has elapsed since the I/O unit has conveyed a memory access request. A first signal may be asserted if the first and second amounts of time have elapsed. A memory subsystem may be transitioned from operating in a full power state to a first low power state responsive to assertion of the first signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.