Implementing storage adapter performance optimization with chained hardware operations and error recovery firmware path
US8656213B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2011 |
| Grant date | Feb 18, 2014 |
| Priority date | — |
| Expiry date | Mar 12, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0793
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and controller for implementing storage adapter performance optimization with a predefined chain of hardware operations configured to minimize hardware and firmware interactions and a bridge code configured to select a firmware sequence for error recovery to complete the operations responsive to an identified error in the predefined chain, and a design structure on which the subject controller circuit resides are provided. A selected predefined chain is configured to implement a particular performance path to maximize performance. Responsive to an identified predefined error during hardware operations in the predefined hardware chain, a bridge code is configured to select a non-performance path firmware sequence for error recovery completion of remaining operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.