Amorphous semiiconductor layer memory device
US8659000B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2011 |
| Grant date | Feb 25, 2014 |
| Priority date | — |
| Expiry date | May 24, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/53
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes: an amorphous semiconductor layer of a first conduction type; a solid electrolyte layer containing movable ions and provided in contact with a part of one of faces of the amorphous semiconductor layer; a first electrode electrically connected to the amorphous semiconductor layer via the solid electrolyte layer; a second electrode electrically connected to one of the faces of the amorphous semiconductor layer; and a third electrode provided over the other face of the amorphous semiconductor layer with an insulating layer therebetween. At the time of application of voltage to the third electrode, at least a part of the amorphous semiconductor layer reversibly changes to a second conduction type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.