Resistive memory and methods for forming the same
US8659090B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2011 |
| Grant date | Feb 25, 2014 |
| Priority date | — |
| Expiry date | Apr 16, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
Abstract
A device includes an active region formed of a semiconductor material, a gate dielectric at a surface of the active region, and a gate electrode over the gate dielectric. A first source/drain region and a second source/drain region are on opposite sides of the gate electrode. A Contact Etch Stop Layer (CESL) is over the first and the second source/drain regions. An Inter-Layer Dielectric (ILD) includes a top surface substantially level with a top surface of the gate electrode. A first contact plug is over and electrically connected to the first source/drain region. A second contact plug is over and aligned to the second source/drain region. The second contact plug and the second source/drain region are spaced apart from each other by a portion of the first CESL to form a capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.