Complementary metal oxide semiconductor transistor and fabricating method thereof
US8659092B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2010 |
| Grant date | Feb 25, 2014 |
| Priority date | — |
| Expiry date | Feb 12, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K85/6572
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fabricating method of CMOS transistor includes following steps. A first gate and a second gate are formed on a substrate. A gate insulator is formed on the substrate to cover the first and second gates. A first source, a first drain, a second source, and a second drain are formed on the gate insulator. The first source and the first drain are above the first gate. The second source and the second drain are above the second gate. A first channel layer and a mask layer are formed on the gate insulator. The mask layer is on the first channel layer. The first channel layer is above the first gate and contacts with the first source and the first drain. A second channel layer is formed on the gate insulator. The second channel layer is above the second gate and contacts with the second source and the second drain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.