Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or controlling same
US8659956B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2011 |
| Grant date | Feb 25, 2014 |
| Priority date | — |
| Expiry date | Mar 30, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of generating a voltage on an integrated circuit device comprising a memory cell array including (i) a plurality of memory cells, arranged in a matrix of rows and columns, and (ii) a plurality of bit lines, wherein each bit line includes a plurality of memory cells. The integrated circuit device further comprises voltage generation circuitry, coupled to a plurality of the bit lines, to (i) apply a first voltage to a first group of associated bit lines, (ii) apply a second voltage to a second group of associated bit lines, (iii) generate a third voltage by connecting the first group of associated bit lines and the second group of associated bit lines, and (iv) output the third voltage. Also, disclosed is a method of operation and/or control of such an integrated circuit device as well as such voltage generation circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.