Patent · US Active

Enhanced power savings for memory arrays

US8659963B2 · kind B2 · utility

3Cited by

9References

18Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Osama Dengler · Eppelheim, DE
Stefan Payer · Stuttgart, DE
Philipp Salz · Eppelheim, DE
Rolf Sautter · Nagold, DE

Key dates

Filing date	Jan 5, 2012
Grant date	Feb 25, 2014
Priority date	—
Expiry date	Apr 25, 2032

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/419
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory array is provided that comprises a plurality of global bit lines such that each bit line is coupled to a plurality of memory cells. The memory array further comprises a plurality of precharge logic such that each precharge logic is coupled to an associated global bit line in the plurality of global bit lines. Identification logic in the memory array is coupled to the plurality of precharge logic. The identification logic provides a precharge enable signal to a subset of the plurality of precharge logic on each clock cycle such that the subset of precharge logic precharges its associated subset of global bit lines to a voltage level of a voltage source, thereby reducing the power consumption of the memory array.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.