Dynamically calibrated DDR memory controller
US8661285B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2011 |
| Grant date | Feb 25, 2014 |
| Priority date | — |
| Expiry date | Aug 16, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DDR memory controller is described wherein a core domain capture clock is created by programmably delaying the core clock of the memory controller. The delay of this capture clock is typically calibrated during a power on the initialization sequence in concert with a DDR memory in a system environment, thereby minimizing the effects of system delays and increasing both device and system yield. An additional embodiment also includes programmably delaying the incoming dqs signal. To compensate for voltage and temperature variations over time during normal operation, a runtime dynamic calibration mechanism and procedure is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.