Castellated gate MOSFET tetrode capable of fully-depleted operation
US8664071B2 · kind B2 · utility
Inventor
Key dates
| Filing date | Mar 19, 2012 |
| Grant date | Mar 4, 2014 |
| Priority date | — |
| Expiry date | Mar 19, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
Abstract
A method of fabricating a castellated-gate MOSFET tetrode device capable of fully depleted operation is disclosed. The device is formed on a semiconductor substrate region having an upper portion with a top surface and a lower portion with a bottom surface. A source region and a drain region are formed by ion implantation into the semiconductor substrate region, with adjoined primary and secondary channel-forming regions also disposed therein between the source and drain regions, thereby forming an integrated cascode structure. A plurality of thin semiconductor channel elements are formed by etching a plurality of spaced gate slots to a first predetermined depth into the substrate. The formation of first, second, and additional gate structures are described in two possible embodiments which facilitate the formation of self-aligned source and drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.