Method of forming a robust, modular MIS (metal-insulator-semiconductor) capacitor with improved capacitance density

US8664076B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Venkat Raghavan · Fryeburg, US
• Andrew Strachan · Santa Clara, US

Key dates

• Filing date: Sep 21, 2011
• Grant date: Mar 4, 2014
• Expiry date: Sep 21, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/716

Abstract

A method of forming a capacitor structure comprises: forming a doped polysilicon layer on an underlying dielectric layer; forming a dielectric stack on the doped polysilicon layer; forming a contact hole in the dielectric stack to expose a surface region of the doped polysilicon layer; forming a conductive contact plug that fills the contact hole and is in contact with the exposed surface of the doped polysilicon layer; forming a plurality of trenches in the dielectric stack such that each trench exposes a corresponding surface region of the doped polysilicon layer; forming a conductive bottom capacitor plate on exposed surfaces of the of the dielectric stack and on exposed surfaces of the doped polysilicon layer; forming a capacitor dielectric layer on the bottom capacitor plate; and forming a conductive top capacitor plate on the capacitor dielectric layer.