Semiconductor device manufacturing method

US8664119B2 · kind B2 · utility

Assignee

• INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES · CN

Inventors

• Huaxiang Yin · Beijing, CN
• Qiuxia Xu · Beijing, CN
• Lingkuan Meng · Beijing, CN
• Dapeng Chen · Beijing, CN

Key dates

• Filing date: Nov 28, 2011
• Grant date: Mar 4, 2014
• Expiry date: Nov 28, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor device manufacturing method, comprising: providing a semiconductor substrate, on which a gate conductor layer as well as a source region and a drain region positioned on both sides of the gate conductor layer are provided, forming an etch stop layer on the semiconductor substrate, forming an LTO layer on the etch stop layer, chemical mechanical polishing the LTO layer, forming an SOG layer on the polished LTO layer, the etch stop layer, LTO layer and SOG layer forming a front metal insulating layer, back etching the SOG layer and etch stop layer of the front metal insulating layer to expose the gate conductor layer, and removing the gate conductor layer.