Nonvolatile memory device

US8664631B2 · kind B2 · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventors

• Jun Hirota · Yokohama, JP
• Yoko Iwakaji · Yokohama, JP
• Moto Yabuki · Tokyo, JP

Key dates

• Filing date: Sep 20, 2011
• Grant date: Mar 4, 2014
• Expiry date: Sep 20, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N70/883

Abstract

According to one embodiment, a nonvolatile memory device includes a word line interconnect layer, a bit line interconnect layer, a pillar, and charge bearing members. The word line interconnect layer includes a plurality of word lines extending in a first direction. The bit line interconnect layer includes a plurality of bit lines extending in a second direction that intersects the first direction. The pillar is disposed between each of the word lines and each of the bit lines. The charge bearing members contain a negative fixed charge, and provided on side faces of the pillars. The pillars includes a diode film provided with a p-type layer and an n-type layer and a variable resistance film stacked on the diode film. The charge bearing member is disposed on side faces of the p-type layer, and is not disposed on side faces of the n-type layer.