High density chip stacked package, package-on-package and method of fabricating the same
US8664757B2 · kind B2 · utility
7Cited by
1References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2011 |
| Grant date | Mar 4, 2014 |
| Priority date | — |
| Expiry date | May 10, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package including a protection layer, a plurality of semiconductor chips stacked on the protection layer, an inner encapsulant disposed on the protection layer to surround side surfaces of the semiconductor chips, and a terminal disposed to be buried in an upper portion of the inner encapsulant. Herein, each of the semiconductor chips includes an active surface, an inactive surface opposite to the active surface, and a chip pad disposed on a portion of the active surface, and an upper surface of the terminal is exposed from an upper surface of the inner encapsulant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.