Connector design for packaging integrated circuits
US8664760B2 · kind B2 · utility
10Cited by
73References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2012 |
| Grant date | Mar 4, 2014 |
| Priority date | — |
| Expiry date | Jan 4, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3841
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.