Non-volatile memory device and read method thereof
US8665643B2 · kind B2 · utility
8Cited by
3References
50Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2012 |
| Grant date | Mar 4, 2014 |
| Priority date | — |
| Expiry date | Apr 28, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a non-volatile memory device which includes a memory cell array having memory cells arranged in rows and columns, a page buffer circuit configured to read data from the memory cell array, and a control logic and input/output interface block including a normal read scheduler controlling a normal read operation and a data recover read scheduler controlling a data recover read operation and configured to control the page buffer circuit at a read request. One of the normal read scheduler and the data recover read scheduler is selected according to selection information provided from an external device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.