Memory edge cell
US8665654B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2013 |
| Grant date | Mar 4, 2014 |
| Priority date | — |
| Expiry date | Jun 21, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A column of a memory includes a first edge cell and at least one memory cell. The first edge cell is located at a first edge of the column and includes a first edge cell reference node and a second edge cell reference node. Each of the at least one memory cells includes a first memory reference node. The first edge cell reference node is coupled to respective first memory reference nodes of the at least one memory cell. The second edge cell reference node serves as second memory reference nodes of the at least one memory cell. Front-end layers of the first edge cell are the same as front-end layers of a memory cell of the at least one memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.