Adaptive equalization using correlation of edge samples with data patterns
US8665940B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 30, 2012 |
| Grant date | Mar 4, 2014 |
| Priority date | — |
| Expiry date | May 30, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/046
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.