Digital pre-distortion with model-based order estimation
US8666336B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 16, 2012 |
| Grant date | Mar 4, 2014 |
| Priority date | — |
| Expiry date | Sep 7, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B17/11
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An embodiment of an integrated circuit is disclosed. This embodiment includes a processor programmed with a behavior model associated with power amplification. A calibration signal generator is coupled to the processor and configured to generate a digital calibration signal. The processor is coupled to receive a digital feedback signal. The processor is configured to determine at least one parameter associated with the power amplification in response to the digital feedback signal using the behavior model. The at least one parameter is selected from a group consisting of a nonlinearity order and a memory length. A digital predistorter is coupled for parameterization responsive to the at least one parameter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.