Signal processing system, integrated circuit comprising buffer control logic and method therefor
US8667190B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2009 |
| Grant date | Mar 4, 2014 |
| Priority date | — |
| Expiry date | Nov 2, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A signal processing system comprising buffer control logic arranged to allocate a plurality of buffers for the storage of information fetched from at least one memory element. Upon receipt of fetched information to be buffered, the buffer control logic is arranged to categorize the information to be buffered according to at least one of: a first category associated with sequential flow and a second category associated with change of flow, and to prioritize respective buffers from the plurality of buffers storing information relating to the first category associated with sequential flow ahead of buffers storing information relating to the second category associated with change of flow when allocating a buffer for the storage of the fetched information to be buffered.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.