Computer system interrupt handling
US8667201B2 · kind B2 · utility
1Cited by
3References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2011 |
| Grant date | Mar 4, 2014 |
| Priority date | — |
| Expiry date | Nov 14, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system, method and article of manufacture for an accelerated processing device (APD) to request a central processing unit (CPU) to process a task, comprising enqueuing a plurality of tasks on a queue using the APD, generating a user-level interrupt and transmitting to the CPU the plurality of tasks in the queue using an interrupt handler associated with a CPU thread.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.