Bypass and insertion algorithms for exclusive last-level caches
US8667222B2 · kind B2 · utility
2Cited by
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18Claims
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Key dates
| Filing date | Apr 1, 2011 |
| Grant date | Mar 4, 2014 |
| Priority date | — |
| Expiry date | Jan 14, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/123
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method are described for implementing an exclusive lower level cache (LLC) policy within a computer processor. For example, one embodiment of a computer processor comprises: a mid-level cache circuit (MLC) for storing a first set of cache lines containing instructions and/or data; a lower level cache circuit (LLC) for storing a second set of cache lines of instructions and/or data; and an insertion circuit for implementing a policy for inserting or replacing cache lines within the LLC based on values of use recency and use frequency associated with the lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.