System and method for clock control for power-state transitions
US8667319B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 16, 2008 |
| Grant date | Mar 4, 2014 |
| Priority date | — |
| Expiry date | Dec 20, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Clock management is implemented using a variety of systems, devices and methods. According to one embodiment a clock transitioning circuit arrangement (104) is implemented for receiving data from a processor system (102) via a data bus (212, 214) and for modifying a state a clock-generation unit (106) having a local memory for controlling a plurality of clock outputs that provide clock signals for use by the processing system (102). The arrangement has a memory circuit (206) for storing the data from the processor system (102) and a control circuit (208) for accessing the data in the memory circuit (206) in response to a request to change a clock signal provided by an output of the plurality of clock outputs and for providing corresponding data to the local memory of the clock generation unit (106).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.