Clock optimization with local clock buffer control optimization

US8667441B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Charles J. Alpert · Cedar Park, US
• Zhuo Li · Austin, US
• Gi-Joon Nam · Austin, US
• David A. Papa · Austin, US
• Chin Ngai Sze · Austin, US
• Natarajan Viswanathan · Austin, US

Key dates

• Filing date: Nov 16, 2010
• Grant date: Mar 4, 2014
• Expiry date: Apr 23, 2031

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2119/12
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A physical synthesis tool for dock optimization with local clock buffer control optimization is provided. The physical synthesis flow consists of delaying the exposure of clock routes until after the clock optimization placement stage. The physical synthesis tool clones first local clock buffers. Then, the physical synthesis tool runs timing analysis on the whole design to compute the impact of this necessarily disruptive step. After cloning local clock buffers, the physical synthesis tool adds an extra optimization step to target the control signals that drive the local clock buffers. This optimization step may includes latch cloning, timing-driven placement, buffer insertion, and repowering. The flow alleviates high-fanout nets and produces significantly better timing going into clock optimization placement. After placement, the physical synthesis tool fixes latches and local clock buffers in place, inserts clock routes, and repowers local clock buffers.