Patent · US Active

Hybrid channel semiconductor device and method for forming the same

US8669155B2 · kind B2 · utility

9Cited by
13References
8Claims
0Family size

Assignee

Inventors

Key dates

Filing dateApr 11, 2011
Grant dateMar 11, 2014
Priority date
Expiry dateApr 11, 2031

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D84/08

Abstract

A hybrid channel semiconductor device and a method for forming the same are provided. The method includes: providing a first semiconductor layer, the first semiconductor layer including an NMOS area and a PMOS area, a surface of the first semiconductor layer being covered by a second semiconductor layer, wherein electrons have higher mobility than holes in one of the first semiconductor layer and the second semiconductor layer, and holes have higher mobility than electrons in the other; forming a first dummy gate structure, and a first source region and a first drain region on respective sides of the first dummy gate structure on the second semiconductor layer in the NMOS area, forming a second dummy gate structure, and a second source region and a second drain region on respective sides of the second dummy gate structure on the second semiconductor layer in the PMOS area; forming an interlayer dielectric layer on the second semiconductor layer and performing planarization; removing the first dummy gate structure and the second dummy gate structure to form a first opening and a second opening; and forming a first gate structure on the one of the first semiconductor layer and the se…

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.