Semiconductor device and manufacturing method thereof
US8669624B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2012 |
| Grant date | Mar 11, 2014 |
| Priority date | — |
| Expiry date | Jul 26, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/68
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are a semiconductor device which enables reduction of diffusion of Si in the manufacturing process of an MIPS element and suppression of an increase in EOT, and a method of manufacturing the same. An embodiment of the present invention is a semiconductor device including a field effect transistor having a gate insulating film provided on a silicon substrate and a gate electrode provided on the gate insulating film. The gate electrode is a stack-type electrode including a conductive layer containing at least Ti, N, and O (oxygen) and a silicon layer provided on the conductive layer, and the concentration of oxygen in the conductive layer is highest in the side of the silicon layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.