System and method of bypassing unrounded results in a multiply-add pipeline unit
US8671129B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2011 |
| Grant date | Mar 11, 2014 |
| Priority date | — |
| Expiry date | Aug 25, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3884
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing unit, system, and method for performing a multiply operation in a multiply-add pipeline. To reduce the pipeline latency, the unrounded result of a multiply-add operation is bypassed to the inputs of the multiply-add pipeline for use in a subsequent operation. If it is determined that rounding is required for the prior operation, then the rounding will occur during the subsequent operation. During the subsequent operation, a Booth encoder not utilized by the multiply operation will output a rounding correction factor as a selection input to a Booth multiplexer not utilized by the multiply operation. When the Booth multiplexer receives the rounding correction factor, the Booth multiplexer will output a rounding correction value to a carry save adder (CSA) tree, and the CSA tree will generate the correct sum from the rounding correction value and the other partial products.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.