Strained channel field effect transistor and the method for fabricating the same
US8673722B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2011 |
| Grant date | Mar 18, 2014 |
| Priority date | — |
| Expiry date | Jan 19, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
Abstract
The present invention discloses a strained channel field effect transistor and a method for fabricating the same. The field effect transistor comprises a substrate, a source/drain, a gate dielectric layer, and a gate, characterized in that, an “L” shaped composite isolation layer, which envelops a part of a side face of the source/drain adjacent to a channel and the bottom of the source/drain, is arranged between the source/drain and the substrate; the composite isolation layer is divided into two layers, that is, an “L” shaped insulation thin layer contacting directly with the substrate and an “L” shaped high stress layer contacting directly with the source and the drain. The field effect transistor of such a structure improves the mobility of charge carriers by introducing stress into the channel by means of the high stress layer, while fundamentally improving the device structure of the field effect transistor and improving the short channel effect suppressing ability of the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.