Semiconductor device with lower metal layer thickness in PMOS region

US8674452B2 · kind B2 · utility

Assignee

• UNITED MICROELECTRONICS CORP. · TW

Inventors

• Chin-Cheng Chien · Tainan, TW
• Tzung-Ying Lee · Lileng, TW
• Tsuo-Wen Lu · Kaohsiung, TW
• Shu-Yen Chan · 埔鹽鄉, TW
• Jei-Ming Chen · Tainan, TW
• Yu-Min Lin · Hsinchu, TW
• Chun-Wei Hsu · Taichung, TW

Key dates

• Filing date: Jun 24, 2011
• Grant date: Mar 18, 2014
• Expiry date: Jan 24, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/685

Abstract

A semiconductor device includes: a substrate having a first region and a second region; a first gate structure disposed on the first region, wherein the first gate structure comprises a first high-k dielectric layer, a first work function metal layer, and a first metal layer disposed between the first high-k dielectric layer and the first work function metal layer; and a second gate structure disposed on the second region, wherein the second gate structure comprises a second high-k dielectric layer, a second work function metal layer, and a second metal layer disposed between the second high-k dielectric layer and the second work function metal layer, wherein the thickness of the second metal layer is lower than the thickness of the first metal layer.