Semiconductor device and structure
US8674470B1 · kind B1 · utility
52Cited by
330References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2012 |
| Grant date | Mar 18, 2014 |
| Priority date | — |
| Expiry date | Dec 22, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second single crystal transistors, the second layer overlying the at least one metal layer; and at least one conductive layer underneath the second layer, the at least one conductive layer is constructed to provide a back-bias to a portion of the plurality of second single crystal transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.