High voltage bipolar transistor with pseudo buried layers

US8674480B2 · kind B2 · utility

Assignee

• SHANGHAI HUA HONG NEC ELECTRONICS CO., LTD. · CN

Inventors

• Tzuyin CHIU · Shanghai, CN
• TungYuan Chu · Shanghai, CN
• Wensheng Qian · Shanghai, CN
• YungChieh Fan · Shanghai, CN
• Jun Hu · Shanghai, CN
• Donghua Liu · Shanghai, CN
• Yukun Lv · Shanghai, CN

Key dates

• Filing date: Dec 13, 2010
• Grant date: Mar 18, 2014
• Expiry date: Dec 13, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/401
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A high voltage bipolar transistor with shallow trench isolation (STI) comprises the areas of a collector formed by implanting first electric type impurities into active area and connected with pseudo buried layers at two sides; Pseudo buried layers which are formed by implanting high dose first type impurity through the bottoms of STI at two sides if active area, and do not touch directly; deep contact through field oxide to contact pseudo buried layers and pick up the collectors; a base deposited on the collector by epitaxial growth and in-situ doped by second electric type impurity, in which the intrinsic base touches local collector and extrinsic base is used for base pick-up; a emitter which is a polysilicon layer deposited on the intrinsic base and doped with first electric type impurities. This invention makes the depletion region of collector/base junction from 1D (vertical) distribution to 2D (vertical and lateral) distribution. The bipolar transistor's breakdown voltages are increased by only enlarge active critical dimension (CD). This is low-cost process.