Wire-based methodology of widening the pitch of semiconductor chip terminals
US8674504B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2012 |
| Grant date | Mar 18, 2014 |
| Priority date | — |
| Expiry date | May 21, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/381
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaged semiconductor device (100) comprising a semiconductor chip (101) of an area having a first surface (101a) including a plurality of bond pads (102) linearly arrayed, adjacent pads having a first pitch (103) center-to-center; an insulating layer (110) on the first chip surface covering the chip area, the layer having a height (116) and a second surface (110a) parallel to the first surface; the second surface including contact nodes (120) in staggered array, the nodes having the same plurality as the pads, adjacent nodes having a second pitch (121) center-to-center greater than the first pitch; and metal wires through the layer height connecting the pads to respective nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.