Device including a plurality of memory banks and a pipeline control circuit configured to execute a command on the plurality of memory banks
US8675419B2 · kind B2 · utility
3Cited by
6References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2011 |
| Grant date | Mar 18, 2014 |
| Priority date | — |
| Expiry date | Dec 7, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a delay buffer, and a pipeline control circuit. The pipeline control circuit controls the delay buffer to hold read data from outputting to a read/write bus for each of banks based on a read command to the each bank while the pipeline control circuit controlling the delay buffer to output write data to the read/write bus, when a next command to the each bank is a write command for the write data. The read/write bus is common to the banks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.