High speed time interleaved sense amplifier circuits, methods and memory devices incorporating the same
US8675434B1 · kind B1 · utility
2Cited by
12References
20Claims
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Key dates
| Filing date | Apr 29, 2012 |
| Grant date | Mar 18, 2014 |
| Priority date | — |
| Expiry date | May 1, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device can include first sense amplifiers coupled to bit lines of a memory array in a first access period and de-coupled from the bit lines in a first sense period, the first sense amplifiers configured to amplify data signals from the memory array in the first sense period; and second sense amplifiers coupled to the bit lines in a second access period that follows the first access period and configured to amplify data signals from the memory cell array in a second sense period that overlaps the first sense period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.