Memory manager for a network communications processor architecture
US8677075B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2012 |
| Grant date | Mar 18, 2014 |
| Priority date | — |
| Expiry date | Sep 2, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/506
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Described embodiments provide a network processor having a plurality of processing modules coupled to a system cache and a shared memory. A memory manager allocates blocks of the shared memory to a requesting one of the processing modules. The allocated blocks store data corresponding to packets received by the network processor. The memory manager maintains a reference count for each allocated memory block indicating a number of processing modules accessing the block. One of the processing modules reads the data stored in the allocated memory blocks, stores the read data to corresponding entries of the system cache and operates on the data stored in the system cache. Upon completion of operation on the data, the processing module requests to decrement the reference count of each memory block. Based on the reference count, the memory manager invalidates the entries of the system cache and deallocates the memory blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.