Methods of fabricating devices including source/drain region with abrupt junction profile
US8679910B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2011 |
| Grant date | Mar 25, 2014 |
| Priority date | — |
| Expiry date | May 21, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/017
Abstract
Provided are methods of fabricating a semiconductor device including a metal oxide semiconductor (MOS) transistor. The methods include forming a gate pattern on a semiconductor substrate. The semiconductor substrate is etched using the gate pattern as an etching mask to form a pair of active trenches spaced apart from each other in the semiconductor substrate. Epitaxial layers are formed in the active trenches, respectively. The respective epitaxial layers are formed by sequentially stacking first and second layers. The first and second layers are formed of a semiconductor layer having a lattice constant greater than the semiconductor substrate, and a composition ratio of the second layer is different from that of the first layer. Semiconductor devices having the first and second layers are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.