Circuit and method for interconnecting stacked integrated circuit dies
US8680582B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2011 |
| Grant date | Mar 25, 2014 |
| Priority date | — |
| Expiry date | Aug 15, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Signals are routed to and from identical stacked integrated circuit dies by selectively coupling first and second bonding pads on each of the dies to respective circuits fabricated on the dies through respective transistors. The transistors connected to the first bonding pads of an upper die are made conductive while the transistors connected to the second bonding pads of the upper die are made non-conductive. The transistors connected to the second bonding pads of a lower die are made conductive while the transistors connected to the first bonding pads of the lower die are made non-conductive. The second bonding pads of the upper die are connected to the second bonding pads of the lower die through wafer interconnects extending through the upper die. Signals are routed to and from the circuits on the first and second dies through the first and second bonding pads, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.