Field effect transistor with buried gate pattern
US8680588B2 · kind B2 · utility
0Cited by
6References
16Claims
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Key dates
| Filing date | Feb 26, 2008 |
| Grant date | Mar 25, 2014 |
| Priority date | — |
| Expiry date | Aug 19, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/711
Abstract
A field effect transistor includes a buried gate pattern that is electrically isolated by being surrounded by a tunneling insulating film. The field effect transistor also includes a channel region that is floated by source and drain regions, a gate insulating film, and the tunneling insulating film. The buried gate pattern and the tunneling insulating film extend into the source and drain regions. Thus, the field effect transistor efficiently stores charge carriers in the buried gate pattern and the floating channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.