Wafer level package with embedded passive components and method of manufacturing
US8680683B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2010 |
| Grant date | Mar 25, 2014 |
| Priority date | — |
| Expiry date | Dec 4, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer level package includes an epoxy layer formed on an adhesive covered substrate during manufacturing for securing electrical components in place prior to being embedded in a molded material. An electrically conductive block is fixed in the epoxy layer. Vias are formed for accessing face up component contacts using a metalized layer on the surface of the molded material. After stripping the adhesive and substrate, the epoxy layer is penetrated to expose electrical contacts for face down components. An electrical connection is made between the face up and face down components using the block. Optionally, a dielectric layer covers the molded material and a second metalized layer placed on the dielectric layer to carry another electrical component embedded in a second dielectric layer covering the first dielectric layer. Thus a stacked component arrangement including multiple die and passive components is effectively fabricated into the wafer level package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.