Column redundancy circuitry for non-volatile memory
US8681548B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2012 |
| Grant date | Mar 25, 2014 |
| Priority date | — |
| Expiry date | May 3, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/78
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a non-volatile memory circuit, techniques are presented so that bad columns can be ignored and/or replaced during memory data input and output operations. A column redundant circuit for this purpose reduces circuit size and improves performance. User data is grouped in an interleaved manner so that data belonging to consecutive logical address will be distributed into different physical locations. For example, all column data can be physically grouped into, say, 5 divisions and user data can be written into or accessed from one division after another consecutively. Each division has its own clock control. The column redundancy block can generate bad column locations' information and send it to control logic to switch the user clock to a different division clock, thereby skipping bad columns. By controlling the clocks for different columns, the user can directly access good columns without touching bad columns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.